Fast Edges

Signal / Power Integrity and High Speed Design

We offer classes from the beginner to the advanced user. One, two and three day classes. Public or private classes at your location. Have presented classes for over 20 years with excellent real world examples. No advanced math is required only general engineering principles. Fast Edges has taught over 5,000 engineers worldwide - from the USA to Brazil to South Korea to Japan to Europe....
This class will allow you to become familiar with signal integrity analysis at the board level. The lecture's modules address transmission lines and their effects on digital circuitry and printed circuit boards. The course will present detailed examples from real-world designs to demonstrate the necessity of understanding signal integrity issues and applying sound signal integrity principles to your PCB Design.

With this course you will gain a better understanding of the following:

Printed circuit boards: -drivers, receivers, Zo, Zdiff, stackup
Termination, topology, timing, parasitics, etc
Differential pair: routing, timing, crosstalk, common mode, terminating, multi-GHz
Crosstalk: microstrip vs stripline, forward & reverse, timing & jitter, understanding and preventing
Power integrity: planes, capacitors – ESL, size, location, mounting inductance
Reference planes: ground, power, return currents, splits, crosstalk, stitch caps
Vias: reference changes, stub lengths, stackup, impedance
Connectors: pinouts for high speed return current & crosstalk
High speed layout: vias, connectors, capacitors, PCB losses, planes
S parameters
Testing issues: equipment, probes, test points
Models: IBIS, drivers, receivers, simulators and accuracy

Audience

Digital Design Engineers
ECAD Designers with some high speed experience
Technicians with High Speed experience
Those who would like to further their knowledge on Printed Circuit Board Signal Integrity issues
No advanced math is needed

Testimonials

" I had attended your recent course at our Philips, Semiconductors site. I have found this to be one of the best training courses I have attended (and believe me I have attended quite a few). The presentation style, material and making use of real life examples made this much more informatative and useful."

3 - 5 day class syllabus 3day_Signal Power Integrity and High Speed Design ClassJan3_18.pdf

What is a transmission line
- What causes transmission lines
- What do they do to digital circuitry
- Avoiding transmission line problems
Transmission line effects
- Undershoot & Overshoot – can destroy boards
- Ringback, monotonicity, crosstalk, timing
Printed circuit boards
- Stackup
- Making controlled Zo not controlled distance
- Crosstalk & diff pair problems with multiple vendors
Drivers, receivers, Zo
- Strength & speed
- Zo & drivers
- Incident vs reflected wave switching
Board interconnect delay
- Different than system delay but important
- Receiver input C, driver output Rs, PCB Zo, etc
- Reflected vs incident wave switching
Termination
- Placement and stub length
- Parallel, series, Zo matching, driver Rs matching
- Diodes - dangerous
Topologies
- When are topologies important
- How do topologies affect signal integrity & timing
- Short & long Tee, star, daisy chain
- Stub length
Package parasitics
- L's, C's, and R's
- Transmission lines in packages
- How do they affect signal integrity & timing
- Capacitive loading on transmission lines
Differential pair
- Noise and EMI
- Layout issues
- Zdiff, Zcomm, Zeven, & Zodd
- Controlling Zdiff
- Side to side vs broadside (over/under)
- Weak vs strong coupling
- Zdiff problems
- Skew affects on signal integrity & timing
- Better terminations
- Pad & antipad issues
- Routing rules
- Controlling mounting & gold finger capacitance
- How to make differential pair for > 3 GHz
Crosstalk
- What causes crosstalk
- Safe routing densities
- Effects on timing & signal integrity
- Microstrip vs Stripline - different
- Side to side vs dual stripline over/under
- FEXT vs NEXT
- Effects of Zo, trace width, spacing, length, guard tracks...
- Differential pair crosstalk
  - Diff pair to diff pair
  - Diff pair to single ended signals
- Fixing crosstalk
- What needs to be done by layout engineers
PCB power integrity
- Planes
  - Power & ground
  - Spacing & location - loop inductance
- Bypass capacitors
  - ESL
  - Package & size µF
  - Spacing to load
  - Location on PCB & empty spaces
  - Mounting inductance, via placement, spacing, pads, etc
Reference planes
- Perforation
- Crossing splits
- Reference consistency in designs
- Vias, layer changes & references
- Controls routing & stackup
- Need to inform layout designers
Connectors
- Controlled Zo, geometry, pinouts
- Reference consistency
- How many grounds & Vccs - return currents
Vias
- Zo changes
- Reference changes
- Stub lengths
- Blind & buried vias
- Pads, antipads, hole diameter
- Loading
- How to make a 10 GHz via
AC losses
- Skin effect
- Dielectric loss - Df
- Microstrip vs stripline
- Noise margins with differential pair
- Pre-emphasis & equalization
- Surface coatings / treatment
Fiber Weave Effect - FWE
- Multi Gb/s problems
- Different weaves, different spacing
- Routing for skew - angles & spacing
- Materials available
Trace surface roughness
- Causes
- Additional losses
- Options from PCB manufactures
S Parameters
- Frequency dependent descriptors
- Good for gigahertz designs
- S21 - Insertion loss or interconnect loss for SI
- Includes discontinuities, connectors, packages
- VNA - 2 & 4 port networks
- S₂₁, S₄₁ & S₃₁
- S_dd21, S_dd41 & S_dd31
Testing issues
- Faster boards are harder to test
- How do you test them
- What equipment & how fast
IBIS models
- Drivers & receivers
- Simulators & accuracy
- Repairing & modifying
- Rs, t_rise / t_fall, input C, parasitics
Layout issues
- How to make quality high speed boards
- What tools are needed
- Signal integrity issues must be included
- PCBs are now part of the design
- Engineer / layout cooperation